IEEE

Implementation of 256-Bit AES and SHA3 on FPGA

Abstract: The work discusses an implementation of the SHA3 algorithm and AES encryption/decryption algorithms which is of 256 bits using Verilog HDL on FPGA. The approach emphasizes optimizing ...
IEEE

Pipelined Implementation of Secure Hash Algorithm on FPGA for Enhanced Performance

Abstract: This paper presents the implementation and opti-mization of the SHA-256 algorithm on an FPGA platform, specif-ically on the Xilinx Artix-4 DDR board. The main objective is to enhance the ...