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3.39 Design a 5-to-32 decoder using 3-to-8 decoder modules as building blocks. Assume each3-to-8 decoder has one active-low enable input, E1, and one active-high enable input, E2.3.40 Realize each of the following sets of functions using a 4-to-16 decoder module and outputlogic gates (choose NAND or AND gates to minimize the fan-in of the output gates).(a)f1(a,b,c,d) = ∑ m(2,4,10,11,12,13)f2(a,b,c,d) = ∏ M(0to3,6to9,12,14,15)f3(a,b,c,d) = bc abd(b)f1(a,b,c,d) = ∑ m(0,1,7,13)f2(a,b,c,d) = abc
3.39 Design a 5-to-32 decoder using 3-to-8 decoder modules as building blocks. Assume each3-to-8 decoder has one active-low enable input, E1, and one active-high enable input, E2.3.40 Realize each of the following sets of functions using a 4-to-16 decoder module and outputlogic gates (choose NAND or AND gates to minimize the fan-in of the output gates).(a)f1(a,b,c,d) = ∑ m(2,4,10,11,12,13)f2(a,b,c,d) = ∏ M(0to3,6to9,12,14,15)f3(a,b,c,d) = bc abd(b)f1(a,b,c,d) = ∑ m(0,1,7,13)f2(a,b,c,d) = abc
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3.39 Design a 5-to-32 decoder using 3-to-8 decoder modules as building blocks. Assume each3-to-8 decoder has one active-low enable input, E1, and one active-high enable input, E2.3.40 Realize each of the following sets of functions using a 4-to-16 decoder module and outputlogic gates (choose NAND or AND gates to minimize the fan-in of the output gates).(a)f1(a,b,c,d) = ∑ m(2,4,10,11,12,13)f2(a,b,c,d) = ∏ M(0to3,6to9,12,14,15)f3(a,b,c,d) = bc abd(b)f1(a,b,c,d) = ∑ m(0,1,7,13)f2(a,b,c,d) = abc
3.39 Design a 5-to-32 decoder using 3-to-8 decoder modules as buildin…
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